Semiconductor device and method for fabricating the same

ABSTRACT

Into a channel formation region of a semiconductor substrate of p-type silicon, indium ions are implanted at an implantation energy of about 70 keV and a dose of about 5×10 13 /cm 2 , thereby forming a p-doped channel layer. Next, germanium ions are implanted into the upper portion of the semiconductor substrate at an implantation energy of about 250 keV and a dose of about 1×10 16 /cm 2 , thereby forming an amorphous layer in a region of the semiconductor substrate deeper than the p-doped channel layer.

RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No.10/676,877 filed Oct. 2, 2003, which is based on Japanese PatentApplication No. JP 2002-297513, filed Oct. 10, 2002 the contents ofwhich are hereby incorporated by reference in their entirety.

BACKGROUND OF THE INVENTION

The present invention relates to MIS semiconductor devices capable ofaccomplishing a further miniaturization and operating with high speedand low power consumption, and to methods for fabricating the same.

With increasing packing density of a semiconductor device, MIStransistors in the device are requested to become miniaturized. Toaccomplish this request, a MIS transistor having a heavily-doped channelstructure in which the dopant concentration of a channel region is madehigh is required (For example, Japanese Unexamined Patent PublicationNo. 08-250729).

Hereinafter, a conventional method for fabricating a MIS transistor willbe described with reference to the accompanying drawings.

FIGS. 13A to 13C, 14A and 14B are sectional views showing process stepsof the conventional method for fabricating a MIS transistor step bystep.

First, as shown in FIG. 13A, indium (In) ions acting as a p-type dopantare implanted into a semiconductor substrate 200 made of p-type siliconat an implantation energy of 100 keV and a dose of about 1×10¹⁴/cm².Thereafter, the resulting substrate is subjected to thermal treatment toform a p-diffused channel layer 203 in a channel formation region of thesemiconductor substrate 200.

As shown in FIG. 13B, a gate oxide film 201 having a thickness of about1.5 nm is then formed on the semiconductor substrate 200. On the gateoxide film 201, a gate electrode 202 is formed which is made ofpolysilicon having a thickness of about 150 nm.

Next, as shown in FIG. 13C, using the gate electrode 202 as a mask,arsenic (As) ions acting as an n-type dopant are implanted into thesemiconductor substrate 200 at an implantation energy of 2 keV and adose of about 5×10¹⁴/cm², thereby forming n-type implantation layers206A. Then, using the gate electrode 202 as a mask, boron (B) ionsacting as a p-type dopant are implanted into the semiconductor substrate200 at an implantation energy of 5 keV and a dose of about 2×10¹³/cm²,thereby forming p-type implantation layers 207A.

As shown in FIG. 14A, an insulating film of silicon nitride or the likehaving a thickness of about 50 nm is deposited on the implantedsemiconductor substrate 200. The deposited insulating film isanisotropically etched to form sidewalls 208 on the side surfaces of thegate electrode 202.

As shown in FIG. 14B, using the gate electrode 202 and sidewalls 208 asa mask, arsenic ions acting as an n-type dopant are implanted into thesemiconductor substrate 200 at an implantation energy of 15 keV and adose of about 3×10¹⁵/cm². The resulting semiconductor substrate 200 issubjected to high-temperature and short-time thermal treatment to formn-diffused source and drain layers 205 in regions of the semiconductorsubstrate 200 located at either side of the sidewalls 208. During thistreatment, in regions of the semiconductor substrate 200 interposedbetween each of the n-diffused source and drain layers 205 and thep-diffused channel layer 203, n-diffused extension layers 206 are formedby the diffusion of the n-type implantation layers 206A. In regions ofthe semiconductor substrate 200 located below the n-diffused extensionlayers 206, p-diffused pocket layers 207 are formed by the diffusion ofthe p-type implantation layers 207A.

As described above, in order to miniaturize the MIS transistor withoutproducing any short channel effect, the conventional fabricating methodof the MIS transistor employs, as a dopant for forming the p-diffusedchannel layer 203, heavy ions of indium (In) having a larger mass numberthan boron (B) and in addition the conventional method has a tendency toincrease the dose of indium ions.

When indium ions of high dose are implanted into the semiconductorsubstrate 200, however, the implanted region of the semiconductorsubstrate 200 is amorphized. This causes, in the subsequent thermaltreatment for activation, formation of EOR (End-of-Range) dislocationloop defect layers (referred simply to as dislocation loop defectlayers) in the vicinity of the lower side of the interface between theamorphous layer and the crystal layer. Indium contained thereinsegregates largely to the dislocation loop defect layers, so that theactivation concentration of the p-diffused channel layer 203 decreases.As a result, the conventional method cannot provide a transistor havinga desired dopant profile.

Moreover, if the dislocation loop defect layers are formed in thep-diffused channel layer 203, leakage current disadvantageously flowsalong the dislocation loop defect layers.

FIG. 15 illustrates the dopant profile of the p-diffused channel layer203 taken along the A-A line in FIG. 13A. FIG. 15 plots the depthmeasured from the substrate surface in ordinate and the logarithm of thedopant concentration of indium in abscissa. As seen from the indium ionprofile of FIG. 15, indium ions contained in the p-diffused channellayer 203 segregate by the thermal treatment to the dislocation loopdefect layers formed in the vicinity of the amorphous-crystal interface.

As is apparent from the above, it is difficult for the conventionalmethod for fabricating a semiconductor device to form a heavily-diffusedchannel layer, which is dispensable for a miniaturized transistor, tohave a desired dopant concentration.

SUMMARY OF THE INVENTION

With the foregoing problems in mind, an object of the present inventionis to ensure an increased dopant concentration of a dopant-diffusedchannel layer of a semiconductor device while the appearance of shortchannel effect accompanied with the miniaturization of the device isavoided, and to suppress an increase in leakage current flow resultingfrom a low threshold voltage and a highly doped channel of the device.

To attain the above object, a method for fabricating a semiconductordevice of the present invention is designed so that first dopant ionswhich are heavy ions for forming a channel are implanted into asemiconductor substrate and then second dopant ions are implantedthereinto, thereby expanding (moving down) an amorphous-crystalinterface to a region of the substrate deeper than a dopant implantationlayer formed by implanting the first dopant ions.

To be more specific, a method for fabricating a semiconductor deviceaccording to the present invention comprises: a first step ofimplanting, into a channel formation region of a semiconductorsubstrate, first dopant ions of a first conductivity type which areheavy ions with a relatively large mass number to form a dopantimplantation layer in the channel formation region; and a second step ofimplanting second dopant ions into the semiconductor substrate to forman amorphous layer expanding from the substrate surface to a region ofthe substrate deeper than the dopant implantation layer.

With the method for fabricating a semiconductor device of the presentinvention, the amorphous-crystal interface is moved down to the positionin the substrate located deeper than that of the dopant implantationlayer. Therefore, even if the subsequent thermal treatment is performedto restore the crystallinity of the substrate, no amorphous-crystalinterface is formed in the dopant implantation layer. This eliminatesthe probability of occurrence of a dislocation loop defect layer in thedopant implantation layer during the thermal treatment after the heavyion implantation, which prevents the phenomenon in which the heavy ionsimplanted in the channel formation region segregate to the dislocationloop defect layer to become inactivated. Moreover, since no dislocationloop defect layer is formed, leakage current flow resulting from thedislocation loop defect layer can be prevented as well.

It is known that even a relatively small dose of heavy ions generallyamorphizes part of a semiconductor substrate because of their masseffect. In the present invention, the amorphous-crystal interface isexpanded deeper than the channel formation region. Therefore, eventhough the heavy ions are implanted into the channel formation region ata higher dose than the extent that the ions induce amorphization of theregion, the heavy ions cause no dislocation loop defect layerimmediately below the channel formation region during the thermaltreatment after the implantation. This suppresses segregation of theheavy ions immediately below the channel formation region, therebyattaining a heavily-doped and abrupt channel formation region with aretrograde profile.

Preferably in the inventive method, the semiconductor substrate is madeof silicon and the second dopant ion belongs to group IV elements.

In this case, the plane orientation of the semiconductor substrate ispreferably the {100} plane.

Also in this case, the semiconductor substrate preferably includes, inthe upper portion thereof, an epitaxial layer formed by epitaxiallygrowing silicon.

Furthermore in this case, the semiconductor substrate preferablyincludes, in the upper portion thereof, a strained silicon layer havinga crystal lattice of a larger lattice constant than a normal latticeconstant.

In the inventive method, the heavy ions are preferably indium ions.

In this case, the dose of the heavy ions to be implanted is preferably5×10¹³/cm² or more.

Preferably, the inventive method further comprises, after the secondstep, a third step of performing a first thermal treatment to diffusethe first dopant ions from the dopant implantation layer, therebyforming a first diffused layer of the first conductivity type in thechannel formation region, a fourth step of selectively forming a gateinsulating film on the semiconductor substrate and a gate electrode onthe gate insulating film, a fifth step of implanting third dopant ionsof a second conductivity type into the semiconductor substrate using thegate electrode as a mask, and a sixth step of performing a secondthermal treatment on the semiconductor substrate to diffuse the thirddopant ions, thereby forming a second diffused layer of the secondconductivity type whose junction position is relatively shallow.

This method forms a diffused extension layer of the second diffusedlayer in the MIS transistor.

In this case, the first thermal treatment is preferably rapid thermalannealing performed at a heating rate of about 100IC/sec or higher, at aheating temperature of 850 to 1050° C., and either with the peaktemperature of the treatment kept for 10 seconds at the maximum or withthe peak temperature not kept.

Preferably, the inventive method further comprises, between the secondand third steps, the step of performing a third thermal treatment atsuch a temperature that the first dopant ions do not diffuse from thedopant implantation layer and that the crystallinity of the amorphouslayer is restored, thereby recovering crystal damages caused by thefirst dopant ions.

This method restores the crystallinity of the semiconductor substratewith implantation damages introduced by the heavy ion implantation inthe first step while the occurrence of residual defects is prevented.

In this case, the heating temperature of the third thermal treatment ispreferably 400 to 600° C. Also in this case, the heating time of thethird thermal treatment is preferably 1 to 20 hours.

Preferably, the inventive method further comprises, between the fourthand sixth steps, the step of implanting fourth dopant ions of the-firstconductivity type into the semiconductor substrate using the gateelectrode as a mask, and the second thermal treatment performed in thesixth step diffuses the fourth dopant ions, thereby forming a thirddiffused layer of the first conductivity type below the second diffusedlayer. With this method, a dopant-diff-used pocket layer made of thethird diffused layer can surely be formed below the second diffusedlayer.

Preferably, the inventive method further comprises, after the sixthstep, the step of forming sidewalls of an insulating film on the sidesurfaces of the gate electrode, and the step of implanting fifth dopantions of the second conductivity type into the semiconductor substrateusing the gate electrode and the sidewalls as a mask and then performinga fourth thermal treatment to diffuse the fifth dopant ions, therebyforming, outside the second diffused layer, a fourth diffused layer ofthe second conductivity type which has a deeper junction interface thanthe second diffused layer.

This method forms diffused source and drain layers in regions of thesemiconductor substrate located at either side of the sidewalls.

A semiconductor device of the present invention comprises: asemiconductor substrate including a diffused channel layer in the upperportion thereof; and a gate electrode formed above the semiconductorsubstrate with a gate insulating film interposed therebetween, and thediffused channel layer is formed by implanting dopant ions which areheavy ions with a relatively large mass number, and the diffused channellayer contains germanium ions.

Preferably in the inventive device, germanium ions are contained also ina region of the semiconductor substrate located below the diffusedchannel layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a sectional view illustrating a construction of a MIStransistor according to a first embodiment of the present invention.

FIGS. 2A through 2C are sectional views showing process steps of afabricating method of a MIS transistor according to the first embodimentof the present invention step by step.

FIGS. 3A through 3C are sectional views showing process steps of thefabricating method of a MIS transistor according to the first embodimentof the present invention step by step.

FIGS. 4A and 4B are sectional views showing process steps of thefabricating method of a MIS transistor according to the first embodimentof the present invention step by step.

FIGS. 5A through 5C are graphs showing dopant profiles in the processsteps illustrated in FIGS. 2A through 2C, respectively.

FIGS. 6A through 6C are sectional views showing process steps of afabricating method of a MIS transistor according to a second embodimentof the present invention step by step.

FIGS. 7A through 7C are sectional views showing process steps of thefabricating method of a MIS transistor according to the secondembodiment of the present invention step by step.

FIGS. 8A through 8C are sectional views showing process steps of thefabricating method of a MIS transistor according to the secondembodiment of the present invention step by step.

FIGS. 9A through 9C are graphs showing dopant profiles in the processsteps illustrated in FIGS. 6A through 6C, respectively.

FIG. 10 is a graph showing a dopant profile in the process stepillustrated in FIG. 7A.

FIG. 11A is a sectional view illustrating a construction of a MIStransistor according to a third embodiment of the present invention.

FIGS. 11B and 11C are diagrams schematically showing processes of thegrowth of a strained silicon layer in the MIS transistor according tothe third embodiment of the present invention.

FIGS. 12A through 12C are sectional views showing process steps of afabricating method of a MIS transistor according to a fourth embodimentof the present invention step by step.

FIGS. 13A through 13C are sectional views showing process steps of aconventional fabricating method of a MIS transistor step by step.

FIGS. 14A and 14B are sectional views showing process steps of theconventional fabricating method of a MIS transistor step by step.

FIG. 15 is a graph showing the relation between the depth measured fromthe substrate surface and the dopant concentration, which is obtainedafter the formation of a diffused channel layer in the conventional MIStransistor.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment

A first embodiment of the present invention will be described below withreference to the accompanying drawings.

FIG. 1 shows a cross-sectional construction of a MIS transistoraccording to the first embodiment of the present invention.

Referring to FIG. 1, a gate insulating film 101 of silicon oxide isformed on the main surface of a semiconductor substrate 100 of p-typesilicon (Si), for example. On the gate insulating film 101, a gateelectrode 102 of polysilicon is formed. On the both side surfaces of thegate electrode 102, sidewalls 108 of silicon nitride are formed.

In a region of the semiconductor substrate 100 located below the gateinsulating film 101, a p-diffused channel layer 103 is formed byimplanting indium (In) ions which are heavy ions with a relatively largemass number.

In a region of the semiconductor substrate 100 deeper than the diffusedchannel layer 103, a germanium (Ge)-containing layer 104 is formed byimplanting ions, such as germanium ions, belonging to group IV elementsby the implantation of which the conductivity of the semiconductorsubstrate 100 will not be changed. In this implantation, as shown inFIG. 5C, the dopant concentration of germanium contained in the deeperside of the diffused channel layer 103 is about 1×10¹⁵ to 1×10 ¹⁷atoms/cm³. On the other hand, the dopant concentration of germaniumcontained in the interface between silicon and the insulating film suchas the gate insulating film 101 or the sidewall 108 is about 5×10¹⁸ to5×10²¹ atoms/cm³, which is very high. Therefore, the transistor shows anabrupt dopant profile.

In regions of the semiconductor substrate 100 located at either side ofthe sidewalls 108, heavily n-diffused layers 105 are formed byimplanting arsenic (As) ions or the like.

In areas of the p-diffused channel layer 103 located below the sidewalls108, heavily n-diffused extension layers 106 are formed by implantingarsenic (As) ions. Below the heavily n-diffused extension layers 106,p-diffused pocket layers 107 are formed which have a higher p-typedopant concentration than the semiconductor substrate 100. Each of thep-diffused pocket layers 107 creates, in the upper side thereof, a PNjunction interface with the corresponding heavily n-diffused extensionlayer 106, thereby preventing a depletion layer from expanding duringthe operation of the transistor.

Hereinafter, a fabricating method of the MIS semiconductor device thusconstructed will be described with reference to the accompanyingdrawings.

FIGS. 2A to 2C, 3A to 3C, 4A and 4B are sectional views showing processsteps of the fabricating method of a MIS transistor according to thefirst embodiment of the present invention step by step.

First, as shown in FIG. 2A, p-type dopant ions with a relatively largemass number, such as indium (In) ions, are implanted into a channelformation region of the semiconductor substrate 100 made of p-typesilicon at an implantation energy of about 70 keV and a dose of about5×10¹³/cm². A p-doped channel layer 103A is thus formed.

Subsequently, as shown in FIG. 2B, germanium (Ge) ions, for example,belonging to group IV elements are implanted into the upper portion ofthe semiconductor substrate 100 at an implantation energy of about 250keV and a dose of about 1×10¹⁶/cm², thereby forming an amorphous layer104A expanding from the substrate surface to a region of thesemiconductor substrate 100 deeper than the p-doped channel layer 103A.Note that the group IV element used in the formation of the amorphouslayer 104A may be silicon instead of germanium. As another substitutefor germanium, a dopant ion exhibiting the same conductivity type as thep-doped channel layer 103A, such as an indium ion, may be used.

In the first embodiment, indium ions are first implanted and thengermanium ions are implanted. Alternatively, germanium ions may first beimplanted and then indium ions may be implanted. In this case, however,because of the pre-amorphous effect caused by the implantation ofgermanium ions, the junction depth of the p-doped channel layer 103Abecomes shallow as compared to that of the ion implantation of indiumions only.

As shown in FIG. 2C, subsequently to the ion implantation of germanium,the semiconductor substrate 100 is heated to about 850 to 1050° C. at aheating rate of about 100° C./sec or more, preferably at about 200°C./sec. After the heating, rapid thermal annealing (RTA) is performedeither with the peak temperature thereof kept for about 10 seconds atthe maximum or with the peak temperature not kept. This RTA diffuses theindium ions contained in the p-doped channel layer 103A into the upperportion of the semiconductor substrate 100 to form the p-diffusedchannel layer 103 as a first diffused layer. Simultaneously with this,the RTA restores the amorphous layer 104A formed by the germanium ionimplantation to a crystalline state. However, since this layer containsgermanium, it is herein referred to as the Ge-containing layer 104. Notethat the RTA with the peak temperature not kept means that the thermaltreatment temperature is lowered on reaching the peak temperature.

Next, as shown in FIG. 3A, the gate insulating film 101 of silicon oxidehaving a thickness of about 1.5 nm is selectively formed on thesemiconductor substrate 100. On the gate insulating film 101, the gateelectrode 102 is selectively formed which is made of polysilicon orpolymetal having a thickness of about 150 nm.

As shown in FIG. 3B, using the gate electrode 102 as a mask, n-typedopant ions such as arsenic (As) ions are implanted into thesemiconductor substrate 100 at an implantation energy of about 3 keV anda dose of about 4×10¹⁴/cm², thereby forming heavily n-doped extensionlayers 106A.

The semiconductor substrate 100 is heated to about 850 to 1050° C. at aheating rate of about 200° C./sec. After the heating, rapid thermalannealing (RTA) is performed either with the peak temperature thereofkept for about 10 seconds at the maximum or with the peak temperaturenot kept. As shown in FIG. 3C, this RTA diffuses the arsenic ionscontained in the heavily n-doped extension layers 106A into portions ofthe semiconductor substrate 100 located at the sides of the gateelectrode 102, thereby forming the heavily n-diffused extension layers106 as second diffused layers which have relatively shallow junctioninterfaces. Moreover, the RTA restores the amorphous layer formed by thearsenic ion implantation to a crystalline state and forms dislocationloop defect layers 109 on the lower side of the amorphous-crystalinterface in the implantation. As a result of the RTA, indium containedin the p-diffused channel layer 103 segregates to the dislocation loopdefect layers 109 as shown in FIG. 3C, whereby the p-diffused pocketlayers 107 as third diffused layers having a higher dopant concentrationthan the p-diffused channel layer 103 are formed below the heavilyn-diffused extension layers 106. The p-diffused pocket layers 107 areformed in a self-aligned manner by the interaction between thedislocation loop defect layers and indium contained in the p-diffusedchannel layer 103.

Thereafter, by chemical vapor deposition (CVD) or the like, a siliconnitride film having a thickness of about 50 nm is deposited on theentire surface of the semiconductor substrate 100 including the gateelectrode 102. The deposited silicon nitride film is anisotropicallyetched to form sidewalls 108 of silicon nitride, as shown in FIG. 4A, onthe both side surfaces of the gate electrode 102 in the direction of thegate length. The sidewalls 108 may be made of silicon oxide instead ofsilicon nitride. As another substitute for silicon nitride, a stackedfilm may be used which is made of silicon oxide and silicon nitride.

Using the gate electrode 102 and sidewalls 108 as a mask, arsenic ionsacting as an n-type dopant are implanted into the semiconductorsubstrate 100 at an implantation energy of about 30 keV and a dose ofabout 3×10¹⁵/cm². The resulting semiconductor substrate 100 is heated toabout 850 to 1050° C. at a heating rate of about 200 to 250° C./sec,after which rapid thermal annealing (RTA) is performed either with thepeak temperature thereof kept for about 10 seconds at the maximum orwith the peak temperature not kept. As shown in FIG. 4B, this RTAdiffuses the arsenic ions into portions of the semiconductor substrate100 located at either side of the sidewalls 108, thereby forming theheavily n-diffused layers 105 as fourth diffused layers which are incontact with the heavily n-diffused extension layers 106, respectively,and which have relatively deep junction interfaces as compared to thelayers 106.

FIGS. 5A to 5C show dopant profiles in the process steps illustrated inFIGS. 2A to 2C, respectively. Each of the figures plots the depthmeasured from the substrate surface in ordinate and the logarithm of thedopant concentration in abscissa.

First, as shown in FIG. 5A, the implantation of indium (In) ions forforming the p-doped channel layer 103A shown in FIG. 2A forms anamorphous-crystal (a/c) interface immediately below the region of thesemiconductor substrate 100 at which the dopant concentration of indiumreaches the peak.

Next, as shown in FIG. 5B, the relatively-deep implantation of germanium(Ge) ions for forming the amorphous layer 104A shown in FIG. 2Btransfers the amorphous-crystal interface to the position in thesemiconductor substrate 100 deeper than the peak position of the dopantconcentration of germanium.

Subsequently, as shown in FIG. 5C, the rapid thermal annealing shown inFIG. 2C restores the amorphous layer 104A formed by the implantations ofindium ions and germanium ions to the crystal layer.

In general, silicon crystals are amorphized when indium ions areimplanted at a dose of about 5×10¹³/cm² or greater. In the firstembodiment, indium ion implantation is performed at a dose of about5×10¹³/cm², so that the amorphous layer 104A is formed in the siliconsubstrate. Taking this into consideration, in the first embodiment,germanium ions which will not change the conductivity type of thesemiconductor substrate 100 are implanted into the semiconductorsubstrate 100 subsequently to the indium ion implantation, so that theamorphous-crystal (a/c) interface is expanded from the regionimmediately below the p-doped channel layer 103A to the deeper position.As a result, the p-diffused channel layer 103 of high dopantconcentration can be formed reliably while no implanted indiumsegregates to the dislocation loop defect layers.

As described above, when the p-diffused channel layer 103 is formed inthe first embodiment, indium ions, which are heavy ions with arelatively large mass number, are implanted at a dose of about5×10¹³/cm², after which germanium ions belonging to the same group asthe element constituting the semiconductor substrate 100 are implantedfor amorphization. Thus, the amorphous-crystal interface formed by theindium implantation can be expanded in the depthwise direction of thesubstrate.

The amorphous-crystal interface is thus expanded in the depthwisedirection of the substrate, whereby the dislocation loop defect layersaffecting diffusion of indium ions are not formed in the vicinity of thep-diffused channel layer 103 during the thermal treatment for formingthe p-diffused channel layer 103 from the p-doped channel layer 103A.Therefore, even though indium ions, which are heavy ions for forming achannel, are implanted at a higher dose than the extent that the ionsinduce amorphization, the conventional phenomenon can be avoided inwhich indium segregates largely to the dislocation loop defect layersand then the activation concentration of the p-diffused channel layer103 is lowered. Accordingly, with the first embodiment, not several-timeimplantations but only one-time implantation of heavy ions for formingthe diffused channel layer can provide a diffused channel layer of highdopant concentration.

Moreover, the implantation of dopant ions belonging to group IV elementsfor amorphization contributes to separation of the amorphous-crystalinterface from the p-diffused channel layer 103, so that no dislocationloop defect layer is formed in the vicinity of the channel region.Therefore, leakage current flow resulting from the dislocation loopdefect layer can be prevented as well.

As is apparent from the above, with the first embodiment, a heavilyp-diffused channel layer 103 containing indium ions which are heavy ionscan be formed reliably in the transistor.

Furthermore, an indium ion with a relatively large mass number is usedin the formation of the p-diffused channel layer 103, so that thevicinity of the substrate surface of the p-diffused channel layer 103has a low dopant concentration while the region thereof slightly deeperthan the substrate surface has a high dopant concentration. That is tosay, a retrograde dopant profile can be provided in this layer. Thisprevents a decrease in carrier mobility mainly resulting from dopantdispersion and minimizes the appearance of short channel effect. As aresult, a transistor including this layer can be miniaturized reliably.

When the arsenic ions are implanted for forming the heavily n-dopedextension layer 106A, part of the semiconductor substrate 100 isamorphized. Thus, the rapid thermal annealing subsequent to the arsenicion implantation forms the dislocation loop defect layers 109 on thelower side of the amorphous-crystal interface. It is known that indiumsegregates largely to the dislocation loop defect layer 109. In thefirst embodiment, indium is used as a dopant ion for the p-diffusedchannel layer 103, so that the region to which indium segregates largelyis formed in the dislocation loop defect layer 109, that is to say, onthe lower side of the junction interface of the heavily n-diffusedextension layer 106. Since this region functions as the p-diffusedpocket layer 107, there is no need to add a formation step of thep-diffused pocket layer 107.

As a method for positively forming the p-diffused pocket layer 107, ap-type dopant may be implanted, subsequently to the arsenic ionimplantation in FIG. 3B, into the semiconductor substrate 100 using thegate electrode 102 as a mask. For example, boron (B) ions acting as ap-type dopant are implanted at an implantation energy of about 10 keVand a dose of about 1×10¹³/cm², which covers a shortage of dopantconcentration of the p-diffused pocket layer 107.

In the first embodiment, an indium ion is used as a dopant ion for thep-diffused channel layer 103. Alternatively, use may be made of an ionwhich is heavier than a boron ion and which acts as a p-type dopant, orboth of the boron ion and the ion which is heavier than the boron ionand which acts as a p-type dopant. As another alternative, a group 3Belement having larger mass number than indium may be used.

In the first embodiment, an n-channel MIS transistor is used as asemiconductor device. Alternatively, a p-channel MIS transistor may beused. For the p-channel MIS transistor, a group 5B element heavier thanan arsenic ion, such as an antimony (Sb) ion or a bismuth (Bi) ion, canbe used as an n-type dopant ion constituting a diffused channel layer.

Second Embodiment

A second embodiment of the present invention will be described belowwith reference to the accompanying drawings.

FIGS. 6A to 6C, 7A to 7C, and 8A to 8C are sectional views showingprocess steps of a fabricating method of a MIS transistor according tothe second embodiment of the present invention step by step.

First, as shown in FIG. 6A, p-type dopant ions with a relatively largemass number, such as indium (In) ions, are implanted into a channelformation region of a semiconductor substrate 100 made of p-type siliconat an implantation energy of about 70 keV and a dose of about5×10¹³/cm². A p-doped channel layer 103A is thus formed.

Subsequently, as shown in FIG. 6B, germanium (Ge) ions, for example,belonging to group IV elements are implanted into the upper portion ofthe semiconductor substrate 100 at an implantation energy of about 250keV and a dose of about 1×10¹⁶/cm², thereby forming an amorphous layer104A expanding from the substrate surface to a region of thesemiconductor substrate 100 deeper than the p-doped channel layer 103A.Also in the second embodiment, the group IV element used in theformation of the amorphous layer 104A may be silicon instead ofgermanium. As another substitute for germanium, a dopant ion exhibitingthe same conductivity type as the p-doped channel layer 103A, such as anindium ion, may be used.

Also in the second embodiment, indium ions are first implanted and thengermanium ions are implanted. Alternatively, germanium ions may first beimplanted and then indium ions may be implanted. As has been describedearlier, in this case, the junction depth of the p-doped channel layer103A becomes shallow as compared to the ion implantation of only indiumions because of the pre-amorphous effect caused by the implantation ofgermanium ions.

As shown in FIG. 6C, subsequently to the ion implantation of germanium,the semiconductor substrate 100 is heated to about 400 to 600° C. andsubjected to thermal treatment for about 1 to 20 hours, preferably for 5to 15 hours. This treatment recovers crystal damages caused by theimplantation of the indium ions while the implanted two-type ions hardlydiffuse. As a result, the amorphous layer 104A changes to aGe-containing layer 104 in a crystalline state. Thus, the thermaltreatment of relatively low temperature and long time is performed onthe amorphous layer 104A, whereby the amorphous layer 104A of thesemiconductor substrate 100 made of silicon regrows into a crystal layer(the Ge-containing layer 104). Such solid phase regrowth is generallyknown as “Solid Phase Epitaxial (SPE) regrowth”. The SPE regrowth beginsat the time the heat with a low temperature of about 400° C. is addedduring heat treatment, and recrystallization proceeds. The diffusioncoefficient of a typical dopant at about 400° C. is sufficiently smallas compared to that of a point defect, so that the dopant hardlydiffuses. Therefore, by performing the relatively low-temperaturethermal treatment for a sufficiently long time, excessive number ofpoint defects present immediately below the amorphous-crystal interfacecan be reduced while the dopant atoms hardly diffuse. In addition, thephase transition from the amorphous layer to the crystal layer can beinduced.

As discussed above, the characteristic of the second embodiment is thatheat treatment of low temperature is performed after the germanium ionimplantation for expanding (moving down) the amorphous-crystalinterface, which is formed by the ion implantation for forming thep-doped channel layer 103A, to the deeper position in the semiconductorsubstrate 100. This restores the crystal structure of the amorphouslayer 104A formed by the implantation of indium and germanium at highdoses. The temperature of this treatment is sufficiently low, so thatdopant dispersion caused by transient enhanced diffusion hardly occursand only the restoration of the crystallinity proceeds. Therefore, theposition of the junction interface of the p-doped channel layer 103A isalmost the same as the position thereof located immediately after theimplantation of indium ions.

As shown in FIG. 7A, subsequently to the thermal treatment, thesemiconductor substrate 100 is heated to about 850 to 1050° C. at aheating rate of about 100° C./sec or more, preferably at about 200°C./sec. After the heating, rapid thermal annealing (RTA) is performedeither with the peak temperature thereof kept for about 10 seconds atthe maximum or with the peak temperature not kept. This RTA diffuses theindium ions contained in the p-doped channel layer 103A into the upperportion of the semiconductor substrate 100 to form the p-diffusedchannel layer 103 as a first diffused layer. The RTA carries out theactivation of the implanted indium ions which cannot be done in thelow-temperature thermal treatment in the step shown in FIG. 6C.

Next, as shown in FIG. 7B, a gate insulating film 101 of silicon oxidehaving a thickness of about 1.5 nm is selectively formed on thesemiconductor substrate 100. On the gate insulating film 101, a gateelectrode 102 is selectively formed which is made of polysilicon orpolymetal having a thickness of about 150 nm.

As shown in FIG. 7C, using the gate electrode 102 as a mask, n-typedopant ions such as arsenic (As) ions are implanted into thesemiconductor substrate 100 at an implantation energy of about 3 keV anda dose of about 4×10¹⁴/cm², thereby forming heavily n-doped extensionlayers 106A.

The semiconductor substrate 100 is heated to about 850 to 1050° C. at aheating rate of about 200° C./sec. After the heating, rapid thermalannealing (RTA) is performed either with the peak temperature thereofkept for about 10 seconds at the maximum or with the peak temperaturenot kept. As shown in FIG. 8A, this RTA diffuses the arsenic ionscontained in the heavily n-doped extension layers 106A into portions ofthe semiconductor substrate 100 located at the sides of the gateelectrode 102, thereby forming heavily n-diffused extension layers 106as second diffused layers which have relatively shallow junctioninterfaces. Moreover, this RTA restores the amorphous layer formed byarsenic ion implantation to a crystalline state and forms dislocationloop defect layers 109 on the lower side of the amorphous-crystalinterface in the implantation. As a result of the RTA, indium containedin the p-diffused channel layer 103 segregates to the dislocation loopdefect layers 109 as shown in FIG. 8A, whereby p-diffused pocket layers107 as third diffused layers having a higher dopant concentration thanthe p-diffused channel layer 103 are formed below the heavily n-diffusedextension layers 106. The p-diffused pocket layers 107 are formed in aself-aligned manner by the interaction between the dislocation loopdefect layers and indium contained in the p-diffused channel layer 103.

Thereafter, by chemical vapor deposition (CVD) or the like, a siliconnitride film of about 50 nm is deposited on the entire surface of thesemiconductor substrate 100 including the gate electrode 102. Thedeposited silicon nitride film is anisotropically etched to formsidewalls 108 of silicon nitride, as shown in FIG. 8B, on the both sidesurfaces of the gate electrode 102 in the direction of the gate length.The sidewalls 108 may be made of silicon oxide instead of siliconnitride. As another substitute for silicon nitride, a stacked film maybe used which is made of silicon oxide and silicon nitride.

Using the gate electrode 102 and sidewalls 108 as a mask, arsenic ionsacting as an n-type dopant are implanted into the semiconductorsubstrate 100 at an implantation energy of about 30 keV and a dose ofabout 3×10¹⁵/cm². The resulting semiconductor substrate 100 is heated toabout 850 to 1050° C. at a heating rate of about 200 to 250° C./sec,after which rapid thermal annealing (RTA) is performed either with thepeak temperature thereof kept for about 10 seconds at the maximum orwith the peak temperature not kept. As shown in FIG. 8C, this RTAdiffuses the arsenic ions into portions of the semiconductor substrate100 located at either side of the sidewalls 108, thereby forming heavilyn-diffused layers 105 as fourth diffused layers which are in contactwith the heavily n-diffused extension layers 106, relatively, and whichhave relatively deep junction interfaces as compared to the layers 106.

FIGS. 9A to 9C and 10 show dopant profiles in the process stepsillustrated in FIGS. 6A to 6C and 7A, respectively. Each of the figuresplots the depth measured from the substrate surface in ordinate and thelogarithm of the dopant concentration in abscissa.

First, as shown in FIG. 9A, the implantation of indium (In) ions forforming the p-doped channel layer 103A shown in FIG. 6A forms anamorphous-crystal (a/c) interface immediately below the region of thesemiconductor substrate 100 at which the dopant concentration of indiumreaches the peak.

Next, as shown in FIG. 9B, the relatively-deep implantation of germanium(Ge) ions for forming the amorphous layer 104A shown in FIG. 6Btransfers the amorphous-crystal interface to the position in thesemiconductor substrate 100 deeper than the peak position of the dopantconcentration of germanium.

Subsequently, as shown in FIG. 9C, the low-temperature thermal treatmentshown in FIG. 6C restores the amorphous layer 104A formed by theimplantations of indium ions and germanium ions to the crystal layer.During this treatment, the implanted indium ions and germanium ionshardly diffuse, and residual defect (dislocation loop defect) layersoccur immediately below the amorphous-crystal interface caused bygermanium ions.

Thereafter, as shown in FIG. 10, the rapid thermal annealing shown inFIG. 7A diffuses indium ions and eliminates the residual defect layerscaused by germanium.

As described above, when the p-diffused channel layer 103 is formed inthe second embodiment, indium ions, which are heavy ions with arelatively large mass number, are implanted at a dose of about5×10¹³/cm², after which germanium ions belonging to the same group asthe element constituting the semiconductor substrate 100 are implantedfor amorphization. Thus, the amorphous-crystal interface formed by theindium implantation can be expanded in the depthwise direction of thesubstrate, so that the dislocation loop defect layers affectingdiffusion of indium ions are not formed in the vicinity of thep-diffused channel layer 103 during the thermal treatment for formingthe p-diffused channel layer 103 from the p-doped channel layer 103A.

Moreover, in the second embodiment, the low-temperature thermaltreatment shown in FIG. 6C is performed between the germanium ionimplantation step shown in FIG. 6B and the high-temperature rapidthermal annealing (spike RTA) step for activating the indium ions shownin FIG. 7A, thereby restoring the crystallinity of the amorphous layer104A. Since the temperature of the low-temperature thermal treatment issufficiently low, crystal damages can be recovered with dopant diffusionhardly occurring. Therefore, only the regrowth of the amorphous layer104A proceeds. As a result, only with the high-temperature rapid thermalannealing, the diffusion depth of indium can positively be madeshallower than that of the first embodiment in which the restoration ofthe crystallinity of the amorphous layer 104A and the activation of theindium ions are performed at the same time.

Therefore, even though indium ions, which are heavy ions for forming achannel, are implanted at a higher dose than the extent that the ionsinduce amorphization, the conventional phenomenon can be avoided inwhich indium segregates largely to the dislocation loop defect layersand then the activation concentration of the p-diffused channel layer103 is lowered. Accordingly, with the second embodiment, notseveral-time implantations but only one-time implantation of heavy ionsfor forming the diffused channel layer can provide a diffused channellayer of high dopant concentration.

Moreover, the implantation of dopant ions belonging to group IV elementsfor amorphization contributes to separation of the amorphous-crystalinterface from the p-diffused channel layer 103, so that no dislocationloop defect layer is formed in the vicinity of the channel region.Therefore, leakage current flow resulting from the dislocation loopdefect layer can be prevented as well.

As is apparent from the above, with the second embodiment, a heavilyp-diffused channel layer 103 containing indium ions which are heavy ionscan be formed reliably in the transistor.

Furthermore, an indium ion with a relatively large mass number is usedin the formation of the p-diffused channel layer 103, so that thevicinity of the substrate surface of the p-diffused channel layer 103has a low dopant concentration while the region thereof slightly deeperthan the substrate surface has a high dopant concentration. That is tosay, a retrograde dopant profile can be provided in the layer. Thisprevents a decrease in carrier mobility mainly resulting from dopantdispersion and minimizes the appearance of short channel effect. As aresult, a transistor including this layer can be miniaturized reliably.

When the arsenic ions are implanted for forming the heavily n-dopedextension layer 106A, part of the semiconductor substrate 100 isamorphized. Thus, the rapid thermal annealing subsequent to the arsenicion implantation forms the dislocation loop defect layers 109 on thelower side of the amorphous-crystal interface. It is known that indiumsegregates largely to the dislocation loop defect layer 109. In thesecond embodiment, indium is used as a dopant ion for the p-diffusedchannel layer 103, so that the region to which indium segregates largelyis formed in the dislocation loop defect layer 109, that is to say, onthe lower side of the junction interface of the heavily n-diffusedextension layer 106. Since this region functions as the p-diffusedpocket layer 107, there is no need to add a formation step of thep-diffused pocket layer 107.

As a method for positively forming the p-diffused pocket layer 107, ap-type dopant may be implanted, subsequently to the arsenic ionimplantation in FIG. 7C, into the semiconductor substrate 100 using thegate electrode 102 as a mask. For example, boron (B) ions acting as ap-type dopant are implanted at an implantation energy of about 10 keVand a dose of about 1×10¹³/cm², which covers a shortage of dopantconcentration of the p-diffused pocket layer 107.

Also in the second embodiment, an indium ion is used as a dopant ion forthe p-diffused channel layer 103. Alternatively, use may be made of anion which is heavier than a boron ion and which acts as a p-type dopant,or both of the boron ion and the ion which is heavier than the boron ionand which acts as a p-type dopant. As another alternative, a group 3Belement having larger mass number than indium may be used.

In the second embodiment, an n-channel MIS transistor is used as asemiconductor device. Alternatively, a p-channel MIS transistor may beused. For the p-channel MIS transistor, group SB element heavier than anarsenic ion, such as an antimony (Sb) ion or a bismuth (Bi) ion, can beused as an n-type dopant ion constituting a diffused channel layer.

The rapid thermal annealing step shown in FIG. 7A may be omitted. Inthis case, the rapid thermal annealing step shown in FIG. 8Asimultaneously forms the p-diffused channel layer 103, the heavilyn-diffused extension layer 106, and the p-diffused pocket layer 107.

In the first and second embodiments, as the semiconductor substrate 100,use may be made of silicon whose plane orientation is the {110} planeinstead of silicon whose plane orientation is a normal plane, or the{100} plane. With the application of the substrate with the {110} plane,indium ions implanted into the substrate are channeled. Therefore, itbecomes difficult to come into collision between the implanted indiumions and silicon crystal lattices constituting the semiconductorsubstrate 100, which weakens damages by the indium ion implantation tothe silicon crystal lattices. As a result, the occurrence ofinterstitial silicon causing EOR dislocation loop defects decreases.

As the semiconductor substrate 100, use may be made of an epitaxialsubstrate in which an epitaxial layer of silicon is formed on the mainsurface of the semiconductor substrate 41. In general, a semiconductorprovided by epitaxial growth excels a normal semiconductor provided bythe crystal pulling method (Czochralski (CZ) method) in crystal quality,so that less number of EOR dislocation loop defects appear in theepitaxial substrate as compared to the number of defects that appears inthe normal semiconductor substrate.

Furthermore, at least a channel region may include a so-called strainedsilicon layer whose silicon crystal lattice has a larger latticeconstant than a normal crystal lattice and the silicon crystal latticeis strained. In the following third embodiment, description will be madeof a concrete example of the device in which the channel region isprovided with the strain silicon layer.

Third Embodiment

A semiconductor device including a strained silicon layer according to athird embodiment of the present invention will be described below withreference to the accompanying drawings.

FIG. 11A shows a cross-sectional construction of a MIS transistoraccording to the third embodiment of the present invention. Thedescription of the components shown in FIGS. 11A to 11C that are thesame as those shown in FIG. 1 will be omitted by retaining the samereference numerals, and only the difference between the two figures willbe described.

Referring to FIG. 11A, a buffer layer 110 of silicon germanium(Si_(1-x)Ge_(x), where 0<x<1) having a thickness of 50 to 100 nm isformed on the main surface of the p-type semiconductor substrate 100. Onthe buffer layer 110, a strained silicon layer 111 having a thickness of20 to 50 nm is formed by epitaxially growing silicon.

As shown in FIG. 11B, when silicon (Si) is epitaxially grown on thebuffer layer 110 having a larger lattice constant than silicon, thelattice constant of the resultant strained silicon layer 111 becomeslarger (strained) than that of a normal silicon as shown in FIG. 11C,resulting in a strained crystal structure. The strained silicon layer111 is thus provided in the channel region of the transistor, whichdecreases the resistances of electrons and holes contained in the regionand enhances the mobilities of the electrons and the holes. Therefore,the operation properties of the transistor are improved.

Note that the buffer layer 110 and the strained silicon layer 111 may begrown not on the main surface of the p-type semiconductor substrate 100but on the main surface of an SOI substrate.

Fourth Embodiment

Next description will be made of a semiconductor device having a raisedsource and drain (raised-s/d) structure according to a fourth embodimentof the present invention, as well as a method for fabricating the same.

FIGS. 12A to 12C are sectional views showing process steps of thefabricating method of a MIS transistor according to the fourthembodiment of the present invention step by step. The description of thecomponents shown in FIGS. 12A to 12C that are the same as those shown inFIGS. 2 to 4 will be omitted by retaining the same reference numerals.

First, as shown in FIG. 12A, a p-diffused channel layer 103 and aGe-containing layer 104 are formed in the upper portion of asemiconductor substrate 100 by the same condition as the fabricatingmethod of a MIS transistor according to the first embodiment. Like thefirst embodiment, a gate insulating film 101 and a gate electrode 102are formed above the main surface of the semiconductor surface 100.Using the gate electrode 102 as a mask, heavily n-diffused extensionlayers 106 are formed in relatively shallow regions of the semiconductorsubstrate 100 and p-diffused pocket layers 107 are formed under theshallow regions. Sidewalls 108 are then formed on the side surfaces ofthe gate electrode 102.

As shown in FIG. 12B, by ultra-high vacuum chemical vapor deposition(UHV-CVD) or the like, epitaxial silicon layers 115 having a thicknessof about 5 to 100 nm, preferably about 35 nm, are selectively grown onthe exposed regions of the main surface of the semiconductor substrate100.

As shown in FIG. 12C, using the gate electrode 102 and the sidewalls 108as a mask, arsenic ions acting as an n-type dopant are implanted intothe epitaxial silicon layers 115 and the semiconductor substrate 100underlying the layers at an implantation energy of about 30 keV and adose of about 3×10¹⁵/cm². The resulting semiconductor substrate 100 isheated to about 850 to 1050° C. at a heating rate of about 200 to 250°C./sec, after which rapid thermal annealing (RTA) is performed eitherwith the peak temperature thereof kept for about 10 seconds at themaximum or with the peak temperature not kept. This RTA diffuses thearsenic ions into portions of the epitaxial silicon layers 115 and thesemiconductor substrate 100 which are located at either side of thesidewalls 108, thereby forming heavily n-diffused layers 105 which arein contact with the heavily n-diffused extension layers 106,respectively, and which have relatively deep junction interfaces ascompared to the layers 106.

Note that the MIS transistor according to the fourth embodiment may befabricated by the fabricating method of the second embodiment.

Also in the fourth embodiment, as the semiconductor substrate 100, usemay be made of a silicon substrate whose plane orientation is the {110}plane or an epitaxial substrate in which an epitaxial layer or astrained silicon layer is provided on the surface of a normalsemiconductor substrate, instead of a silicon substrate whose planeorientation is the {100} plane that is in common use.

In the embodiments described above, the sidewalls 108 are formeddirectly on the side surfaces of the gate electrode 102. Alternatively,an offset spacer of silicon oxide to be used for a mask for extensionimplantation may be formed between the gate electrode 102 and each ofthe side walls 108.

The film used for the sidewalls 108 is not limited to a single-layerfilm. Alternatively, a multilayer film may be employed which is made ofa silicon oxide film having an L-shaped section and a silicon nitridefilm formed on the silicon oxide film.

In the embodiments described above, as the thermal treatment, the rapidthermal annealing is employed either with the peak temperature of thetreatment kept for 10 seconds at the maximum or with the peaktemperature not kept. Alternatively, flash lamp annealing or laserannealing may be employed which is capable of performing a thermaltreatment for a short time.

1-17. (canceled)
 18. A semiconductor device comprising: a gateinsulating film on a semiconductor substrate; a gate electrode on thegate insulating film; a diffused channel layer of a first conductivitytype including a first dopant and formed below a region of the gateinsulating film in the semiconductor substrate; and agermanium-containing layer formed in a region deeper than the diffusedchannel layer in the semiconductor substrate.
 19. The semiconductordevice of claim 18, wherein the diffused channel layer containsgermanium.
 20. The semiconductor device of claim 19, wherein thediffused channel layer has a lower dopant concentration of germaniumthan the first dopant.
 21. The semiconductor device of claim 18, whereinthe first dopant includes heavy ions with a large mass number.
 22. Thesemiconductor device of claim 18, wherein the first dopant includesindium.
 23. The semiconductor device of claim 18, wherein an interfacebetween the gate insulating film and the semiconductor substrate has ahigher dopant concentration of germanium than a lower side of thediffused channel layer.
 24. The semiconductor device of claim 18,wherein a dopant concentration of germanium contained in an interfacebetween the gate insulating film and the semiconductor substrate isabout 5×10¹⁸ to 5×10²¹ atoms/cm³ and the dopant concentration ofgermanium contained in a lower side of the diffused channel layer isabout 1×10¹⁵ to 1×10¹⁷ atoms/cm³.
 25. The semiconductor device of claim18, wherein a region of the diffused channel layer slightly deeper thana surface of the semiconductor substrate has a higher dopantconcentration of the first dopant than the surface of the semiconductorsubstrate.
 26. The semiconductor device of claim 18, further comprising:sidewalls formed on side surfaces of the gate electrode; and diffusedextension layers of a second conductivity type including a second dopantand formed below the sidewalls in the semiconductor substrate, whereinthe diffused extension layers contain germanium.
 27. The semiconductordevice of claim 26, further comprising: diffused pocket layers of thefirst conductivity type including the first dopant and formed below thediffused extension layers in the semiconductor substrate, wherein thediffused pocket layers have a higher dopant concentration of the firstdopant than the diffused channel layer.
 28. The semiconductor device ofclaim 26, further comprising: heavily diffused extension layers of asecond conductivity type including a third dopant, formed below a sideregion of the sidewalls in the semiconductor substrate, connected to thediffused extension layers and having a junction deeper than the diffusedextension layers, wherein the heavily diffused extension layers containgermanium.
 29. The semiconductor device of claim 28, wherein thegermanium-containing layer is formed to a region deeper than the heavilydiffused extension layers.
 30. The semiconductor device of claim 18,wherein the plane orientation of the semiconductor substrate is the{100} plane.
 31. The semiconductor device of claim 18, wherein thesemiconductor substrate comprises silicon.
 32. The semiconductor deviceof claim 18, wherein the semiconductor substrate includes, in the upperportion thereof, an epitaxial layer formed by epitaxially growingsilicon.
 33. The semiconductor device of claim 18, wherein thesemiconductor substrate includes, in the upper portion thereof, astrained silicon layer having a crystal lattice of a larger latticeconstant than a normal lattice constant.
 34. The semiconductor device ofclaim 18, wherein the semiconductor substrate includes: a buffer layercontaining silicon germanium and formed in the upper portion of thesemiconductor substrate; and a strained silicon layer formed on thebuffer layer.